In the recent years, more high-tech electronic devices offer lighter, thinner, and smaller features with friendly operation and multiple functions. In order to meet the requirements of smaller footprints with higher densities, 3D stacking technologies were developed such as POP (Package-On-Package) and DOD (Die-On-Die). One of the POP semiconductor devices is to vertically stack a plurality of leadframe-based semiconductor packages. The leadframe-based POP semiconductor devices using leadframes as chip carriers have the lowest overall cost where the external leads extending from the encapsulants are vertically formed and soldered together to achieve electrical connections. However, the soldered joints between the external leads are vulnerable to break due to CTE mismatch leading to electrical open.
As shown in FIG. 1 and FIG. 2, a conventional leadframe-based POP semiconductor device 100 primarily comprises a first semiconductor package 110 and at least a second semiconductor package 120 stacked above the top of the first semiconductor package 110 where the first semiconductor package 110 and the second semiconductor package 120 are leadframe-based packages for flash memory assembly or DDR memory assembly to increase memory capacities or to add more functions for logic devices, memory devices or other devices. The first semiconductor package 110 comprises a first encapsulant 111, a first chip 112, and a plurality of first external leads 113 (parts of a leadframe) where the first external leads 113 are configured for mounting to a printed circuit board 140 by solder paste 150. The related leadframe packages are TSOP (Thin Small Outline Package), QFP (Quad Flat Package), TQFP (Thin QFP), etc.
The second semiconductor package 120 comprises a second encapsulant 121, a second chip 122 inside the second encapsulant 121, and a plurality of second external leads 123 (parts of another leadframe) where the second external leads 123 of the second semiconductor package 120 are extended and exposed from the second encapsulant 121. Conventionally, the second external leads 123 have exposed portions which are approximately perpendicular to the marking surface of the second encapsulant 121 and are soldered to the soldered regions of the first external leads 113 of the first semiconductor package 110 by soldering materials 130 such as solder paste. Since the soldered joints, where the soldering materials 130 are disposed, between the first external leads 113 and the second external leads 123 are individually formed, therefore, the soldered joints will easily break during TCT (Temperature Cycling Test). After FA (Failure Analysis), the breaks of the soldered joints between the first external leads 113 and the second external leads 123 are due to mis-match of CTE (Coefficient of Temperature Expansion) inside the first semiconductor packages 110 and the second semiconductor package 120. For example, the CTE of the first encapsulant 111 of the first semiconductor package 110 and the second encapsulant 121 of the second semiconductor package 120 are 10 ppm/° C. when below Tg (Glass transition temperature) and 36 ppm/° C. when above Tg where the normal Tg of EMC encapsulant is around 120° C. However, the materials of normal leadframes such as the first external leads 113 and the second external leads 123 are metal or alloy such as Alloy 42 where the CTE is around 4.3 ppm/° C. There is an order difference between the CTE of the leadframe such as Alloy 42 and the one of the first encapsulant 111 and the second encapsulant 121. When the temperature of the conventional leadframed-based POP semiconductor device 100 becomes higher due to operation, the volume expansion of the first encapsulant 111 and the second encapsulant 121 will be much larger than the corresponding ones of the leadframes, i.e., the first external leads 113 and the second external leads 123 where the expansion differences due to higher temperatures will induce stresses at the second external leads 123 from contacts of the first encapsulant 111 and the second external leads 121, as shown in FIG. 1. Therefore, the soldered joints of the second external leads 123 will experience concentrated stresses, especially the second external leads 123 located at the edges of the second semiconductor package 120 leading to soldering breaks.